The present invention is related to integrated circuit (IC) devices and processes of making IC devices. More particularly, the present invention relates to a method for using a hybrid stack to increase source/drain patterning precision.
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Various methods of forming transistors on a semiconductor substrate are known in the art. For example, one method of forming transistors on a silicon substrate involves the well known Local Oxidation of Silicon (LOCOS) process.
A conventional LOCOS process typically includes the following simplified steps. First, a silicon nitride layer is provided on the silicon substrate. Next, using a lithography and etch process, the nitride layer is selectively removed to produce a pattern where transistor source/drain areas are to be located. After patterning the source/drain areas, a field oxide is grown. As oxide growth is inhibited where the nitride layer still remains, the oxide only grows on the silicon substrate exposed during the source/drain patterning step. Finally, after oxide growth is complete, the remaining portions of the nitride layer are removed leaving only the oxidized source/drain areas on the exposed silicon substrate.
Imprecise control of the transistor forming process limits an IC manufacturer""s ability to increase transistor density. A significant source of imprecision is derived from the lithography and etch process. Thus, to increase transistor density, IC manufacturer""s are forced to purchase advanced equipment or to develop lithography and etch processes that allow increased precision from existing equipment. It is desirable to use either existing 365 nm or 248 nm lithography to achieve high density transistors using the LOCOS process.
To increase precision from existing lithography equipment, understanding the lithography and etch process and its limitations is essential. Generally, the process steps include: (1) placing a layer of photoresist over an existing nitride layer, (2) exposing the photoresist to radiation through a mask containing the transistor source/drain pattern, (3) developing the photoresist to define the source/drain pattern on the nitride layer, (4) etching away and removing the nitride layer defined by the developed photoresist, and (5) stripping off the remaining photoresist to leave a patterned nitride layer.
During the radiation exposure step, areas adjacent to the source/drain pattern can be unintentionally exposed to reflected radiation. Exposure to reflected radiation is increased if the thickness of the nitride layer is not accurately controlled. This uncontrolled exposure to reflected radiation limits source/drain pattern precision and, ultimately, transistor density. FIGS. 1A-D, cross-sectional views of pattern imprecision resulting from nitride layer reflectivity, show a portion 10 of an integrated circuit including a photoresist layer 20, a silicon nitride layer 25 and an underlying layer 65. The portion 10 illustrates four undesirable characteristics of apertures in the photoresist layer 20: (1) a footed aperture 30 (FIG. 1A), (2) an undercut aperture 40 (FIG. 1B), (3) a re-entrant aperture 50 (FIG. 1C), and (4) a tapered aperture 60 (FIG. 1D). The undesirable aperture characteristics shown in the portion 10 are the result of radiation reflected during the radiation exposure step. The unpredictable occurrence of the aperture characteristics limits transistor density. The undesirable aperture characteristics generally do not occur simultaneously and are shown in FIGS. 1A-D as examples of types of problems which may occur.
Various methods for reducing or compensating for reflected radiation have been developed. For example, it is known in the art that careful control of nitride layer thickness reduces reflected radiation variance. With the radiation variance reduced, compensation for reflected radiation is more easily attained. However, controlling nitride layer thickness requires the nitride layer to be grown or deposited very slowly. This slow process rate reduces production throughput and increases costs.
Other methods for reducing nitride layer reflectivity involve application of an anti-reflective coating (ARC) between the nitride layer and the photoresist. The ARC material is selected for its ability to absorb radiation during the exposure step. Thus, by applying the ARC, radiation which would ordinarily be reflected by the nitride layer is absorbed by the ARC. In general, two types of ARCs are used: (1) organic ARCs and (2) inorganic ARCs. While use of either type of ARC significantly reduces problems related to reflectivity, both types have drawbacks. For example, organic ARCs are typically very dirty, difficult to apply uniformly, and difficult to remove. These drawbacks result in high defect densities, and consequently reduced yields.
Inorganic ARCs, such as silicon oxynitride (SiON), are generally preferable to organic ARCs because use of inorganic ARCs results in considerably lower defect densities. While use of inorganic ARCs yields lower defect densities, inorganic ARCs can oxidize often during the LOCOS oxidation step. ARC layer oxidation is detrimental as the process of removing an oxidized ARC layer also removes oxidized source/drain areas. Thus, to avoid removing oxidized source/drain areas, the inorganic ARC layer must be removed prior to the oxidation step. However, removing the inorganic ARC before oxidation causes pitting on the surface of the exposed semiconductor substrate which results in defects.
Thus, there is a need for a high throughput IC processing method which reduces reflectivity related problems while minimizing introduction of additional defects.
One embodiment of the invention relates to a method of manufacturing an integrated circuit (IC). The method includes providing a hybrid stack, providing an IC structure pattern over the hybrid stack, and selectively removing a portion of the hybrid stack according to the IC structure pattern. The hybrid stack includes a top layer and a bottom layer and is disposed over an underlying layer. The selectively removing step is performed such that a protective portion of the bottom layer remains over the underlying layer. The protective portion acts to minimize damage to the underlying layer during the selectively removing step. After the selectively removing step, the method continues by removing the protective portion, building oxide structures on the underlying layer, and removing remaining portions of the hybrid stack.
Another embodiment also relates to a method of manufacturing an integrated circuit (IC). The method includes providing a hybrid stack, providing an IC structure pattern over the hybrid stack, selectively removing a portion of the hybrid stack to expose the underlying layer according to the IC structure pattern, building oxide structures on the exposed underlying layer, and removing remaining portions of the hybrid stack. The hybrid stack includes a top layer of silicon nitride and a bottom layer of silicon oxynitride and is disposed over an underlying layer.
Another embodiment of the invention relates to an integrated circuit prepared by a LOCOS process by providing a hybrid stack, providing an IC structure pattern over the hybrid stack, and selectively removing a portion of the hybrid stack according to the IC structure pattern. The hybrid stack includes a top layer and a bottom layer and is disposed over an underlying layer. The selectively removing step is performed such that a protective portion of the bottom layer remains over the underlying layer. The protective portion acts to minimize damage to the underlying layer during the selectively removing step. After the selectively removing step, the method continues by removing the protective portion, building oxide structures on the underlying layer, and removing remaining portions of the hybrid stack.
Yet another embodiment of the invention relates to an integrated circuit manufactured using LOCOS by providing a hybrid stack, providing an IC structure pattern over the hybrid stack, selectively removing a portion of the hybrid stack to expose the underlying layer according to the IC structure pattern, building oxide structures on the exposed underlying layer, and removing remaining portions of the hybrid stack. The hybrid stack includes a top layer of silicon nitride and a bottom layer of silicon oxynitride and is disposed over an underlying layer. The removing remaining portions step minimizes damage to the oxide structures during removal of the remaining portions of the hybrid stack.